library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt60_sec is
	port(clk_sec:in std_logic;--clock signal (1Hz)
		set_sec:in std_logic;--set time enable
		clr:in std_logic;--clear
		qin_sec:in std_logic_vector(7 downto 0);--8421 code from set entity
		qout_sec:out std_logic_vector(7 downto 0);--output 8421 code
		carry_sec:out std_logic;--carry bit for min
		);
end cnt60_sec;

architecture func of cnt60_sec is
	signal temp1:std_logic_vector(3 downto 0);--right digit
	signal temp10:std_logic_vector(3 downto 0);--left digit
begin
		process(set_sec,clk_sec,clr)
		begin
			if(clr='1') then
				temp1<="0000";
				temp10<="0000";
				carry_sec<='0';
			elsif(set_sec='1') then
				temp10<=qin_sec(7 downto 4);
				temp1<=qin_sec(3 downto 0);
				carry_sec<='0';
			elsif(clk_sec'event and clk_sec='1') then
				if(temp1=9) then
					temp1<="0000";
					if(temp10=5) then
						temp10="0000";
						carry_sec<='1';
					else
						temp10<=temp10+1;
						carry_sec<='0';
					end if;
				else
					temp1<=temp1+1;
					carry_sec<='0';
			end if;
			qout_sec<=temp10 & temp1;
		end process;
end func;